1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and its structure. More particularly, the invention relates to a method of manufacturing a semiconductor device comprising a plurality of MOS transistors having different widths of a sidewall oxide film of a gate electrode, and a structure of a semiconductor device.
2. Description of the Background Art
In order to lower the cost of manufacturing LSIs and to increase the operation speed of LSIs, the scale down and high integration of LSIs have been proceeded. However, as such scale down is advanced, a variety of parasitic factors inhibit higher speed of operation. Among those, a main factor to decrease the operation speed of a circuit is a parasitic capacity formed by a gate electrode, a gate insulating film and an extension in a MOS transistor (hereinafter referred to as xe2x80x9cgate overlap capacityxe2x80x9d in the present specification).
To reduce the gate overlap capacity, it is necessary to reduce the amount of overlap between a gate electrode and an extension in plan view (i.e., the degree of overlap between the gate electrode and extension when viewed from above). As a technique to reduce the amount of overlap, it can be considered that an ion implantation for forming an extension is performed at a low energy. However, there is a limit of lowering the energy of ion implantation because when the depth of an extension decreases with a decrease in energy, the parasitic resistance increases and the amount of delay of operation speed increases.
FIG. 36 is a sectional view illustrating a conventional structure of a semiconductor device. A silicon oxide film 102 is formed on a main surface of a silicon substrate 101. A first MOS transistor (the transistor on the left side as viewed in FIG. 36) is formed in a first region of the silicon substrate 101, and a second MOS transistor (the transistor on the right side as viewed in FIG. 36) is formed in a second region of the silicon substrate 101.
The first MOS transistor comprises a gate structure 107 made up of a polysilicon film 103, tungsten silicide film 104, silicon nitride film 105 and sidewall oxide film 106; sidewall 108, extensions 114, source/drain region 115. The second MOS transistor comprises a gate structure 113 made up of a polysilicon film 109, tungsten silicide film 110, silicon nitride film 111 and sidewall oxide film 112; sidewall 108, extensions 116, source/drain region 117. The sidewall oxide films 106 and 112 have the same width. The spaced interval between the paired extensions 114 is the same as that between the paired extensions 116.
FIGS. 37 to 40 are sectional views illustrating a sequence of steps in a conventional method of manufacturing a semiconductor device. Referring to FIG. 37, a silicon oxide film 102 is formed on a main surface of a p-type silicon substrate 101, and a polysilicon film, a tungsten silicide film and a silicon nitride film are formed in the order named on the silicon oxide film 102. These layers are then patterned. Thereby, a structure that a polysilicon film 103, tungsten silicide film 104 and silicon nitride film 105 are stacked in the order named is formed in a first region of the silicon substrate 101, and a structure that a polysilicon film 109, tungsten silicide film 110 and silicon nitride film 111 are stacked in the order named is formed in a second region of the silicon substrate 101.
Referring to FIG. 38, by using these structures as an implantation mask, an n-type impurity 124 is implanted into the silicon substrate 101 through the silicon oxide film 102, thereby forming extensions 114 and 116.
Referring to FIG. 39, the side surfaces of the polysilicon films 103 and 109 are oxidized to form sidewall oxide films 106 and 112. The width of portions of the sidewall oxide films 106 and 112, which are formed inside from the original side surfaces of the polysilicon films 103 and 109, is approximately half of the width of the sidewall oxide films 106 and 112. Thus, the formation of the sidewall oxide films 106 and 112 by oxidizing the side surfaces of the polysilicon films 103 and 109 decreases the length (gate length) of the polysilicon films 103 and 109, thereby permitting a decrease in the amount of overlap between the extensions 114, 116 and the polysilicon films 103, 109.
Referring to FIG. 40, a sidewall 108 is formed on the side surfaces of the gate structures 107 and 113. By using the gate structures 107, 113 and the sidewall 108 as an implantation mask, an n-type impurity is implanted into the silicon substrate 101 through the silicon oxide film 102, to form source/drain regions 115 and 117. Through the foregoing steps, the structure shown in FIG. 36 is obtained.
In LSIs, various kinds of circuits are formed on a semiconductor substrate. Consider the case that a first MOS transistor shown in FIG. 36 constitutes a circuit on which current driving capability is emphasized, and a second MOS transistor shown in FIG. 36 constitutes a circuit on which operation speed is emphasized. For the second MOS transistor, it is desirable that the overlap capacity be reduced as much as possible by minimizing the amount of overlap between a polysilicon film 109 and an extension 116. For the first MOS transistor, it is unnecessary that the overlap capacity is excessively reduced at the sacrifice of current driving capability.
However, with the conventional method of manufacturing a semiconductor device, the sidewall oxide film 106 of the first MOS transistor has the same width as the sidewall oxide film 112 of the second MOS transistor. This results in the same effect of reducing the amount of overlap between polysilicon films 103, 109 and extensions 114, 116. It is therefore difficult to individually comply with demand of a circuit characteristic on which emphasis is placed.
According to a first aspect of the invention, a method of manufacturing a semiconductor device comprises the steps of: (a) preparing a substrate of a first conductivity type; (b) forming a first structure having a first conductive layer formed on a main surface of the substrate with an insulating film between, in a first region of the substrate; (c) forming a second structure having a second conductive layer formed on the main surface of the substrate with an insulating film between, in a second region of the substrate; (d) forming a first sidewall oxide film of a first width by oxidizing a side surface of the first conductive layer; (e) forming a second sidewall oxide film of a second width wider than the first width by oxidizing a side surface of the second conductive layer; (f) forming paired first impurity regions of a second conductivity type sandwiching therebetween the substrate underling the first structure, in the main surface in the first region of the substrate; and (g) forming paired second impurity regions of the second conductivity type sandwiching therebetween the substrate underling the second structure, in the main surface in the second region of the substrate, wherein the amount of overlap between the second conductive layer and the second impurity region in plan view is smaller than the amount of overlap between the first conductive layer and the first impurity region in plan view.
According to a second aspect of the invention, the method of the first aspect is characterized in that the steps (d) and (e) have the steps of: (de-1) forming a third sidewall oxide film by oxidizing the side surface of the first conductive layer, and forming a fourth sidewall oxide film by oxidizing the side surface of the second conductive layer; (de-2) removing the third sidewall oxide film; and (de-3) forming the first sidewall oxide film by oxidizing the side surface of the first conductive layer after removing the third sidewall oxide film, and forming the second sidewall oxide film by oxidizing the side surface of the second conductive layer provided with the fourth sidewall oxide film.
According to a third aspect of the invention, the method of the second aspect is characterized in that the step (f) is performed, after the step (de-2), by introducing impurity of the second conductivity type into the main surface in the first region of the substrate by using the first structure as a mask.
According to a fourth aspect of the invention, the method of the second aspect is characterized in that the step (f) is performed, before the step (de-2), by introducing impurity of the second conductivity type into the main surface in the first region of the substrate by using the first structure as a mask.
According to a fifth aspect of the invention, the method of the second aspect is characterized in that the step (g) is performed, after the step (de-3), by introducing impurity of the second conductivity type into the main surface in the second region of the substrate by using the second structure as a mask.
According to a sixth aspect of the invention, the method of the fifth aspect is characterized in that in the step (g) the impurity is introduced into the main surface in the first region of the substrate.
According to a seventh aspect of the invention, the method of the second aspect is characterized in that the steps (f) and (g) are performed in one step after the step (de-3).
According to an eighth aspect of the invention, the method of the first aspect is characterized in that the first and second conductive layers are semiconductor layers, and that the method further comprises the steps of: (x) forming a first metal layer on the first conductive layer; and (y) forming a second metal layer on the second conductive layer.
According to a ninth aspect of the invention, the method of the first aspect is characterized in that the first and second conductive layers are semiconductor layers, and that the method further comprises the steps of: (x) forming a first metal-semiconductor compound layer by performing silicide formation reaction of the first conductive layer; and (y) forming a second metal-semiconductor compound layer by performing silicide formation reaction of the second conductive layer.
According to a tenth aspect of the invention, a semiconductor device comprises a substrate of a first conductivity type; a first structure having a first conductive layer formed on a main surface in a first region of the substrate with an insulating film between; a second structure having a second conductive layer formed on the main surface in a second region of the substrate with an insulating film between; a first sidewall oxide film of a first width formed on a side surface of the first conductive layer; a second sidewall oxide film of a second width larger than the first width formed on a side surface of the second conductive layer; paired first impurity regions of a second conductivity type sandwiching therebetween the substrate underling the first structure and being formed in the main surface in the first region of the substrate; and paired second impurity regions of the second conductivity type sandwiching therebetween the substrate underling the second structure and being formed in the main surface in the second region of the substrate, wherein the amount of overlap between the second conductive layer and the second impurity region in plan view is smaller than the amount of overlap between the first conductive layer and the first impurity region in plan view.
According to an eleventh aspect of the invention, the semiconductor device of the tenth aspect is characterized in that the first and second conductive layer are semiconductor layers, that the first structure further having a first metal layer formed on the first conductive layer, and that the second structure further having a second metal layer formed on the second conductive layer.
According to a twelfth aspect of the invention, the semiconductor device of the tenth aspect is characterized in that the first and second conductive layers are semiconductor layers, and that the semiconductor device further comprises: a first metal-semiconductor compound layer formed on the first conductive layer; and a second metal-semiconductor compound layer formed on the second conductive layer.
In the first aspect, the first sidewall oxide film of the first width is formed in the first region of the substrate, and the second sidewall oxide film of the second width is formed in the second region of the substrate. Therefore, the amount of overlap between the first impurity region and the first conductive layer in the first region of the silicon substrate can be different from that between the second impurity region and second conductive layer in the second region.
In the second aspect, the first and second sidewall oxide films having different widths can be formed appropriately.
In the third aspect, the spaced interval between the paired first impurity regions can be narrowed, permitting an increase in current driving capability.
In the fourth aspect, the spaced interval between the paired first impurity regions can be widened, so that the effective channel length is increased and the gate overlap capacity is further reduced.
The fifth aspect enables to lower the amount of overlap between the second conductive layer and second impurity region in plan view.
The sixth aspect enables to omit the step of forming a photoresist on the first region of the substrate.
The seventh aspect enables to omit the step of successively forming a photoresist on the first and second regions of the substrate.
In the eighth aspect, the formation of the first and second metal layers enables to decrease the gate resistance.
In the ninth aspect, the formation of the first and second metal-semiconductor compound layers enables to decrease the gate resistance.
In the tenth aspect, since the spaced interval between the paired first impurity regions is narrower than that between the paired second impurity regions, a semiconductor element formed in the first region of the substrate can be used as a transistor constituting such a circuit that the emphasis is on current driving capability. On the other hand, since the spaced interval between the paired second impurity regions is wider than that between the paired first impurity regions, a semiconductor element formed in the second region of the substrate can be used as a transistor constituting such a circuit that the emphasis is on operation speed.
In the eleventh aspect, the presence of the first and second metal layers enables to decrease the gate resistance.
In the twelfth aspect, the presence of the first and second metal-semiconductor compound layers enables to decrease the gate resistance.
It is an object of the present invention to overcome the foregoing problem by providing a method of manufacturing a semiconductor device with which it is able to individually adjust the effect of reducing the overlap capacity between a gate electrode and extensions, according to demand of a circuit characteristic on which emphasis is placed, as well as a structure of a semiconductor device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.